The present invention relates to a demodulator for a frequency shift keying signal and, more particularly, to a demodulator for a frequency shift keying signal which is implemented by a digital circuit only.
As well known in the art a demodulator for a frequency shift keying signal (hereinafter an "FSK demodulator"), usually comprises a frequency discriminator which uses a double-tuning circuit, or a pulse-count type demodulating circuit.
The problem with a double-tuning circuit is that due to the use of an inductance-capacitance (LC) circuit it requires troublesome adjustment and, moreover, involves many factors which have to be taken into consideration in the event of circuit design and, therefore, render the design complex. Such factors are, for example, the characteristics which are affected by temperature, and delay distortion attributable to the circuit.
The pulse-count type demodulating circuit, although simpler in construction than the double-tuning circuit, has shortcoming in regard to high frequency applications because demodulation sensitivity is proportional to pulse width which decreases with measuring frequency. In addition, since the amplitude characteristic of output signals of the pulse-count type circuit depends upon the characteristic of a lowpass filter which is adapted for pulse interpolation, through consideration must be given to the signal rate and the bandwidth at the designing stage.